MULTI-DIE SYSTEM PERFORMANCE OPTIMIZATION

• Main Authors: SADOWSKI, Greg, KUSHNIR, Stephen, SUNDARAM, Sriram, BRANTLEY, William C, SCHULTE, Michael J
• Format: Patent
• Language: English
• Published: 30.12.2021
• Subjects: CALCULATING; COMPUTING; CONTROLLING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS; REGULATING; SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.