MECHANICAL PUNCHED VIA FORMATION IN ELECTRONICS PACKAGE AND ELECTRONICS PACKAGE FORMED THEREBY

• Main Authors: Nishihara, Youichi, Kapusta, Christopher James
• Format: Patent
• Language: English
• Published: 02.12.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall.