ARBITRATION SCHEME FOR COHERENT AND NON-COHERENT MEMORY REQUESTS

A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The clie...

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Main Authors BRANOVER, Alexander J, TSIEN, Benjamin, ARORA, Sonu
Format Patent
LanguageEnglish
Published 24.06.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Abstract A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.
AbstractList A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The client module buffers coherent and non-coherent memory requests and releases the memory requests based on one or more conditions of the processor or one of its caches. The memory requests are released to a central data fabric and into the system based on a first watermark associated with the coherent memory buffer and a second watermark associated with the non-coherent memory buffer.
Author BRANOVER, Alexander J
TSIEN, Benjamin
ARORA, Sonu
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Snippet A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module...
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SubjectTerms CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Title ARBITRATION SCHEME FOR COHERENT AND NON-COHERENT MEMORY REQUESTS
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