MEMORY DEVICE

A memory device includes a plurality of bit lines extending in a first direction, a plurality of lower memory cells below the bit lines and connected to the plurality of bit lines, and a plurality of upper memory cells above the plurality of bit lines and connected to the plurality of bit lines. The...

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Bibliographic Details
Main Author KWON, Yongjin
Format Patent
LanguageEnglish
Published 01.04.2021
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory device includes a plurality of bit lines extending in a first direction, a plurality of lower memory cells below the bit lines and connected to the plurality of bit lines, and a plurality of upper memory cells above the plurality of bit lines and connected to the plurality of bit lines. The memory device comprises a plurality of cell array regions and a plurality of bit line contact regions alternately stacked in the first direction, the plurality of upper memory cells and the plurality of lower memory cells are located in the cell array regions, and only one of either the plurality of upper memory cells or the plurality of lower memory cells are arranged in at least one of the bit line contact regions.
Bibliography:Application Number: US202016859191