Coprocessors with Bypass Optimization, Variable Grid Architecture, and Fused Vector Operations

• Main Authors: Kesiraju, Aditya, Balasubramanian, Srikanth, Kanapathipillai, Pradeep, Alvarez-Heredia, Boris S, Beaumont-Smith, Andrew J, Chachick, Ran A
• Format: Patent
• Language: English
• Published: 27.08.2020
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

In an embodiment, a coprocessor may include a bypass indication which identifies execution circuitry that is not used by a given processor instruction, and thus may be bypassed. The corresponding circuitry may be disabled during execution, preventing evaluation when the output of the circuitry will...