DYNAMIC REDUNDANCY FOR MEMORY

• Main Authors: Wordeman, Matthew R, Worledge, Daniel, Jabeur, Kotb, DeBrosse, John K
• Format: Patent
• Language: English
• Published: 06.08.2020
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; INFORMATION STORAGE; PHYSICS; STATIC STORES

A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.