PERIPHERAL BASED MEMORY SAFETY SCHEME FOR MULTI-CORE PLATFORMS

A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and...

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Main Authors HOOGERBRUGGE, Jan, NIKOV, Ventzislav, MEDWED, Marcel
Format Patent
LanguageEnglish
Published 04.06.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Abstract A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and a memory safety peripheral configured to receive a pointer request, wherein the pointer is a low-fat pointer and to verify that the pointer request is within required memory bounds
AbstractList A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and a memory safety peripheral configured to receive a pointer request, wherein the pointer is a low-fat pointer and to verify that the pointer request is within required memory bounds
Author HOOGERBRUGGE, Jan
MEDWED, Marcel
NIKOV, Ventzislav
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Snippet A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the...
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SubjectTerms CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Title PERIPHERAL BASED MEMORY SAFETY SCHEME FOR MULTI-CORE PLATFORMS
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