III-V CMOS CO-INTEGRATION

A method of fabricating an n-type field effect transistor device (nFET) in a region of a wafer element is provided. The method includes forming a mandrel in the region and growing III-V semiconductor materials on the mandrel. The method also includes pulling the mandrel from a gate space in which a...

Full description

Saved in:
Bibliographic Details
Main Authors Mo, Renee T, Lee, Ko-Tao, Cheng, Cheng-Wei, Tsai, HsinYu
Format Patent
LanguageEnglish
Published 07.05.2020
Subjects
Online AccessGet full text

Cover

Loading…