SHARED BIT LINE ARRAY ARCHITECTURE FOR MAGNETORESISTIVE MEMORY

• Main Authors: HOANG, Loc, LEVI, Amitay
• Format: Patent
• Language: English
• Published: 27.06.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

A magnetoresistive memory architecture in one aspect includes a plurality of bit lines each coupled to two or more respective columns of magnetoresistive memory cells, and a plurality of source lines each coupled to a respective one of the columns of memory cells. A given memory cell can be accessed...