CORE OFF SLEEP MODE WITH LOW EXIT LATENCY

• Main Authors: V, Ramachandiran, IDGUNJI, Sachin, YUE, Lordson, KULSHRESTHA, Narayan, DEWEY, Thomas E
• Format: Patent
• Language: English
• Published: 30.05.2019
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL; PHYSICS

An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the a...