INTEGRATED CIRCUIT PACKAGE WITH MICROSTRIP ROUTING AND AN EXTERNAL GROUND PLANE

Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related...

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Main Author Goh, Eng Huat
Format Patent
LanguageEnglish
Published 04.10.2018
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Abstract Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit structure may include a package substrate having an internal ground plane and a microstrip signal layer as the top metallization layer, and an external ground plane on the surface of the package substrate that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit structure may further include changes to microstrip transmission line geometry to match impedance values of areas covered by the external ground plane with impedance values of areas not covered by the external ground plane.
AbstractList Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit structure may include a package substrate having an internal ground plane and a microstrip signal layer as the top metallization layer, and an external ground plane on the surface of the package substrate that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit structure may further include changes to microstrip transmission line geometry to match impedance values of areas covered by the external ground plane with impedance values of areas not covered by the external ground plane.
Author Goh, Eng Huat
Author_xml – fullname: Goh, Eng Huat
BookMark eNrjYmDJy89L5WTw9_QLcXUPcgxxdVFw9gxyDvUMUQhwdPZ2dHdVCPcM8VDw9XQO8g8OCfIMUAjyDw3x9HNXcPRzAWIF14gQ1yA_Rx8Fd6AEUCjAx9HPlYeBNS0xpziVF0pzMyi7uYY4e-imFuTHpxYXJCan5qWWxIcGGxkYWhhZmJlbmjsaGhOnCgBDNzGm
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US2018286797A1
GroupedDBID EVB
ID FETCH-epo_espacenet_US2018286797A13
IEDL.DBID EVB
IngestDate Fri Jul 19 15:44:44 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US2018286797A13
Notes Application Number: US201715473317
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181004&DB=EPODOC&CC=US&NR=2018286797A1
ParticipantIDs epo_espacenet_US2018286797A1
PublicationCentury 2000
PublicationDate 20181004
PublicationDateYYYYMMDD 2018-10-04
PublicationDate_xml – month: 10
  year: 2018
  text: 20181004
  day: 04
PublicationDecade 2010
PublicationYear 2018
RelatedCompanies Intel Corporation
RelatedCompanies_xml – name: Intel Corporation
Score 3.1737282
Snippet Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS
RESONATORS
SEMICONDUCTOR DEVICES
Title INTEGRATED CIRCUIT PACKAGE WITH MICROSTRIP ROUTING AND AN EXTERNAL GROUND PLANE
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181004&DB=EPODOC&locale=&CC=US&NR=2018286797A1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_GFPVNp-LHlIDSt6Jr09o-DOnST93a0rW6t2FnCoJ0w1X8972ETfe0h0BygZBccne55PILwC26HPQeDZ9qGqgC6UwzVduwNbWqONd03cSFLW50R7EZFvRpYkxa8Ll-CyNxQn8kOCJK1AzlvZH6evF_iOXK2MrlXfmBpPmjn_ddZeUdo7kSk-4O-l6auAlTGOsXYyXOZJ0mwOUeHPSVdsRGWiDtey8D8S5lsWlU_EPYTbG9ujmCFq87sM_Wf691YG-0uvLG7Er6lseQCPzaIHNQ2RAWZayIcpI67NkJPPIa5SFBlmbJOM-ilAi44ygOiBO7mIg3kci3QyLC7JGUDp3YO4Eb38tZqGLPpn-MmBbjzWHop9Cu5zU_A4LbtNKmWo9rtKQWp3Zl9maWRatKNyz7_e0cuttauthefQkHoihD2GgX2s3XN79CU9yU15KDvzdUhD8
link.rule.ids 230,309,786,891,25594,76903
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3fS8MwED7GFOebTsUfUwPK3oquTbv2YUiXdmtd15au1b0NO1MQpBuu4r_vJWy6pz0ESg5Ccund5UsuXwDuEXLQRwx8iqGjC6Rz1VAs3VKVouBc1TQDf2xxojsODS-jz1N9WoPPzV0YyRP6I8kR0aLmaO-V9NfL_00sR-ZWrh7yD6xaPA3SntNeo2MMV2LSnX7PjSMnYm3GetmkHSZSpgpyua6NWGmvi6BQgqWXvriXstwOKoMj2I-xvbI6hhovm9Bgm7fXmnAwXh954-fa-lYnEAn-2mFio7MhzE9Y5qckttnIHrrk1U89gipNokma-DERdMd-OCR26GAh7lQy3wZEpNljVRzYoXsKdwM3ZZ6CPZv9KWKWTbaHoZ1BvVyU_BwILtNyi6odrtKcmpxahdGZmyYtCk03rfe3C2jtaulyt_gWGl46DmaBH46u4FCIZDobbUG9-vrm1xiWq_xGavMXi36HKQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=INTEGRATED+CIRCUIT+PACKAGE+WITH+MICROSTRIP+ROUTING+AND+AN+EXTERNAL+GROUND+PLANE&rft.inventor=Goh%2C+Eng+Huat&rft.date=2018-10-04&rft.externalDBID=A1&rft.externalDocID=US2018286797A1