CACHE AFFINITY AND PROCESSOR UTILIZATION TECHNIQUE

• Main Authors: Chitlur Srinivasa Venkatesh Babu, Corsi Christopher Joseph, Kimmel Jeffrey S
• Format: Patent
• Language: English
• Published: 08.03.2018
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A cache affinity and processor utilization technique efficiently load balances work in a storage input/output (I/O) stack among a plurality of processors and associated processor cores of a node. The storage I/O stack employs one or more non-blocking messaging kernel (MK) threads that execute non-bl...