PINCHED DOPED WELL FOR A JUNCTION FIELD EFFECT TRANSISTOR (JFET) ISOLATED FROM THE SUBSTRATE

A JFET structure may be formed such that the channel region is isolated from the substrate to reduce parasitic capacitance. For example, instead of using a deep well as part of a gate structure for the JFET, the deep well may be used as an isolation region from the surrounding substrate. As a result...

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Bibliographic Details
Main Authors Melanson John L, Tarabbia Marc L, Pan Shanjen
Format Patent
LanguageEnglish
Published 12.10.2017
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES
MICROSTRUCTURAL TECHNOLOGY
PERFORMING OPERATIONS
SEMICONDUCTOR DEVICES
TRANSPORTING
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Summary:A JFET structure may be formed such that the channel region is isolated from the substrate to reduce parasitic capacitance. For example, instead of using a deep well as part of a gate structure for the JFET, the deep well may be used as an isolation region from the surrounding substrate. As a result, the channel in the JFET may be pinched laterally between doped regions located between the source and the drain of the JFET. In other example embodiments, the channel may be pinched vertically and the isolation between the JFET structure and the substrate is maintained. A JFET structure with improved isolation from the substrate may be employed in some embodiments as a low-noise amplifier. In particular, the low-noise amplifier may be coupled to small signal devices, such as microelectromechanical systems (MEMS)-based microphones.
Bibliography:Application Number: US201615093574