METHOD OF FABRICATING PMOS DEVICES WITH EMBEDDED SIGE

• Main Authors: LI Ming, ZUO Qingyun, ZENG Shaohai
• Format: Patent
• Language: English
• Published: 27.07.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method of fabricating PMOS devices with embedded SiGe is disclosed. Prior to the selective epitaxial growth of SiGe, Ge element is implanted to the source/drain recesses and an annealing process is performed to form a strained SiGe alloy layer. Then, the strained SiGe alloy layer is used as a base layer on which another strained SiGe alloy layer is grown continually by an selective epitaxy process, so as to avoid a direct contact between the epitaxially grown strained SiGe alloy layer and the silicon substrate and reduce the defects formed at the SiGe/Si interfaces. Therefore, the stress can be applied to the PMOS channel regions without causing junction current leakage due to the defects at the SiGe/Si interfaces, which enhances the electrical performance of the PMOS devices. The fabrication method is also compatible with the conventional CMOS process.