APPARATUS AND METHOD FOR MULTI-BIT ERROR DETECTION AND CORRECTION

An apparatus and method are described for multi-bit error correction and detection. For example, one embodiment of a processor comprises: error detection logic to detect one or more errors in data when reading the data from a storage device, the data being read from the storage device with parity co...

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Bibliographic Details
Main Authors Bradford Dennis R, Hickmann Brian J, Wu Wei
Format Patent
LanguageEnglish
Published 29.06.2017
Subjects
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