APPARATUS AND METHOD FOR MULTI-BIT ERROR DETECTION AND CORRECTION

• Main Authors: Bradford Dennis R, Hickmann Brian J, Wu Wei
• Format: Patent
• Language: English
• Published: 29.06.2017
• Subjects: BASIC ELECTRONIC CIRCUITRY; CALCULATING; CODE CONVERSION IN GENERAL; CODING; COMPUTING; COUNTING; DECODING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; INFORMATION STORAGE; PHYSICS; STATIC STORES

An apparatus and method are described for multi-bit error correction and detection. For example, one embodiment of a processor comprises: error detection logic to detect one or more errors in data when reading the data from a storage device, the data being read from the storage device with parity codes and error correction codes (ECCs); error correction logic to correct the errors detected by the error detection logic; and a matrix usable by both the error detection logic to detect the one or more errors and the error correction logic to correct the errors, the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region.