INTEGRATED CIRCUIT INCORPORATING A LOW POWER DATA RETIMING CIRCUIT

• Main Authors: Nallani Chakravartula, Aboulhouda Samir, Malladi Ramana Murty
• Format: Patent
• Language: English
• Published: 08.12.2016
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections that use components based on bipolar technology for operating at a relatively higher frequency. The data retiming circuit includes a clock recovery circuit wherein a voltage controlled oscillator provides a recovered clock to a clock generator circuit for generating a latched clock that is provided to a phase detector and a data serializer. The data serializer operates as a synchronous multiplexer for generating a retimed data output signal from a pair of latched data input signals. The phase detector and the data serializer operate in a half-rate mode wherein high and low voltage levels of the latched clock are used for clocking data. The half-rate mode of operation permits the use of a clock frequency that is half that of an input data rate.