POWER EFFICIENT PROCESSOR ARCHITECTURE

In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the...

Full description

Saved in:
Bibliographic Details
Main Authors Makineni Srihari, Herdrich Andrew J, Illikkal Rameshkumar G, Iyer Ravishankar, Moses Jaideep, Srinivasan Sadogopan
Format Patent
LanguageEnglish
Published 13.10.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

Abstract In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
AbstractList In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
Author Makineni Srihari
Iyer Ravishankar
Herdrich Andrew J
Srinivasan Sadogopan
Illikkal Rameshkumar G
Moses Jaideep
Author_xml – fullname: Makineni Srihari
– fullname: Herdrich Andrew J
– fullname: Illikkal Rameshkumar G
– fullname: Iyer Ravishankar
– fullname: Moses Jaideep
– fullname: Srinivasan Sadogopan
BookMark eNrjYmDJy89L5WRQC_APdw1ScHVz83T2dPULUQgI8nd2DQ72D1JwDHL28AxxdQ4JDXLlYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBoZmRpaWpqYWjobGxKkCAFudJpo
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
Physics
ExternalDocumentID US2016299558A1
GroupedDBID EVB
ID FETCH-epo_espacenet_US2016299558A13
IEDL.DBID EVB
IngestDate Fri Jul 19 15:43:47 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US2016299558A13
Notes Application Number: US201615134756
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161013&DB=EPODOC&CC=US&NR=2016299558A1
ParticipantIDs epo_espacenet_US2016299558A1
PublicationCentury 2000
PublicationDate 20161013
PublicationDateYYYYMMDD 2016-10-13
PublicationDate_xml – month: 10
  year: 2016
  text: 20161013
  day: 13
PublicationDecade 2010
PublicationYear 2016
RelatedCompanies Intel Corporation
RelatedCompanies_xml – name: Intel Corporation
Score 3.0626051
Snippet In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core...
SourceID epo
SourceType Open Access Repository
SubjectTerms CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Title POWER EFFICIENT PROCESSOR ARCHITECTURE
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161013&DB=EPODOC&locale=&CC=US&NR=2016299558A1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_G_HzTqvgxpaDkrbg2zawPRVzaMoWtpWt1b6OtKQjSDVvx3_cSO93THnOBfMHd_S65-wXghlrF4M1UtKGZMGxGMyPrC2pYGUV0iy7zt75iPBmMUvt5xmYd-FjVwiie0G9FjogaVaC-N8peL_8vsTyVW1nf5u8oWjwEieuRNjpG-IKQhnhD149CL-SEczedkkms-tDyMuY8Yqy0JYG0ZNr3X4ayLmW57lSCA9iOcLyqOYSOqDTY46u_1zTYHbdP3hrsqBzNokZhq4f1EZAofPVjHUHmk7wkSvQoDjkeZRjr8vUHzRGX6QzHcB34CR8ZOPX8b6fzdLq-TnoC3WpRiVPQc0nN5tilSZ3MFvfM6ZeOKJnF0P_cmWV5Br1NI51v7r6AfdmUJtmkPeg2n1_iEn1tk1-pI_oBU2F8Qw
link.rule.ids 230,309,786,891,25594,76903
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR3LTsJAcELwgTdFDSpqE01vjZTtQj00RrYloNA2pVVuTYvbxMQUYmv8fWfXopy4ziSzu5PM-7EAt6S76L3pcm1owjWDkkRLOpxo3YSgd4sm83e-Yur2RpHxNKfzGnysZ2HkntBvuRwRJWqB8l5Kfb36T2LZsreyuEvfEbR8GIaWrVbRMbov6NKo9sByfM_2mMqYFc1UN5A41LyUmo8YK-30MSiUwdLLQMylrDaNyvAQdn2kl5dHUON5Exps_fdaE_anVcm7CXuyR3NRILCSw-IYVN97dQIFncyxSBKFih94DFnpBYqo_qA6YqKd4QRuhk7IRhoeHf-9NI5mm_ckp1DPlzlvgZKK1WymkenETAx-T81OZvKMdinan76eZWfQ3kbpfDv6GhqjcDqJJ2P3-QIOBEqoZ520oV5-fvFLtLtleiXZ9QNH038t
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=POWER+EFFICIENT+PROCESSOR+ARCHITECTURE&rft.inventor=Makineni+Srihari&rft.inventor=Herdrich+Andrew+J&rft.inventor=Illikkal+Rameshkumar+G&rft.inventor=Iyer+Ravishankar&rft.inventor=Moses+Jaideep&rft.inventor=Srinivasan+Sadogopan&rft.date=2016-10-13&rft.externalDBID=A1&rft.externalDocID=US2016299558A1