PARALLEL VIA TO IMPROVE THE IMPEDANCE MATCH FOR EMBEDDED COMMON MODE FILTER DESIGN

• Main Authors: Chen Chung-Hao Joseph, Zhu Jianfang Olena, Yepes Ana M
• Format: Patent
• Language: English
• Published: 29.09.2016
• Subjects: BASIC ELECTRONIC CIRCUITRY; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PRINTED CIRCUITS; RESONATORS

A parallel via design is disclosed to improve the impedance match for embedded common mode choke filter designs. Particularly suited to such designs on four-layer printed circuit boards, the parallel via design effectively suppresses the reflection of the differential pair. By connecting the vias in parallel, the inductance of the entire via structure is reduced while its capacitance is simultaneously increased. By properly choosing the number of parallel vias and the spacing between them, the impedance of the parallel vias can be well controlled within the frequency range of interest. Consequently, the impedance match can be improved and the return loss of a four-layer printed circuit board common mode choke filter design is reduced.