APPARATUS AND METHOD FOR CONTROLLING LEVEL 0 CACHE
Disclosed herein is an apparatus and method for controlling level 0 caches, capable of delivering data to a processor without errors and storing error-free data in the caches even when soft errors occur in the processor and caches. The apparatus includes: a level 0 cache #0 connected to the load/sto...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
04.08.2016
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| Subjects | |
| Online Access | Get full text |
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| Abstract | Disclosed herein is an apparatus and method for controlling level 0 caches, capable of delivering data to a processor without errors and storing error-free data in the caches even when soft errors occur in the processor and caches. The apparatus includes: a level 0 cache #0 connected to the load/store unit of a first processor; a level 0 cache #1 connected to the load/store unit of a second processor; and a fault detection and recovery unit for reading from and writing to tag memory, data memory, and valid bit memory of the level 0 cache #0 and the level 0 cache #1, performing the write-back and flush of the level 0 cache #0 and the level 0 cache #1 based on information stored therein, and instructing the load/store units of the first and second processors to stall a pipeline and to restart an instruction #n. |
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| AbstractList | Disclosed herein is an apparatus and method for controlling level 0 caches, capable of delivering data to a processor without errors and storing error-free data in the caches even when soft errors occur in the processor and caches. The apparatus includes: a level 0 cache #0 connected to the load/store unit of a first processor; a level 0 cache #1 connected to the load/store unit of a second processor; and a fault detection and recovery unit for reading from and writing to tag memory, data memory, and valid bit memory of the level 0 cache #0 and the level 0 cache #1, performing the write-back and flush of the level 0 cache #0 and the level 0 cache #1 based on information stored therein, and instructing the load/store units of the first and second processors to stall a pipeline and to restart an instruction #n. |
| Author | HAN JIN-HO KWON YOUNG-SU |
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| Snippet | Disclosed herein is an apparatus and method for controlling level 0 caches, capable of delivering data to a processor without errors and storing error-free... |
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| Title | APPARATUS AND METHOD FOR CONTROLLING LEVEL 0 CACHE |
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