ECC BYPASS USING LOW LATENCY CE CORRECTION WITH RETRY SELECT SIGNAL

• Main Authors: GOODMAN BENJIMAN L, WRIGHT KENNETH L, RETTER ERIC E, LASTRAS-MONTANO LUIS A
• Format: Patent
• Language: English
• Published: 30.04.2015
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and,...