ADDRESS TRANSLATION/SPECIFICATION FIELD FOR HARDWARE ACCELERATOR

Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software,...

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Bibliographic Details
Main Authors SWANBERG RANDAL C, RIDER SCOT H, HAVERKAMP FRANK, VOGT JOERG-STEPHAN, JACOBI CHRISTIAN, SETHI VIKRAMJIT
Format Patent
LanguageEnglish
Published 15.01.2015
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.
Bibliography:Application Number: US201414501524