Enhanced FinFET Process Overlay Mark

An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed o...

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Bibliographic Details
Main Authors CHEN MENG-WEI, HSIEH CHI-WEN, LIU CHIAU, CHEN KUEI-SHUN, CHANG CHI-KANG
Format Patent
LanguageEnglish
Published 18.12.2014
Subjects
APPARATUS SPECIALLY ADAPTED THEREFOR
BASIC ELECTRIC ELEMENTS
CINEMATOGRAPHY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.
Bibliography:Application Number: US201414472018