APPARATUS AND METHODS RELATING TO A MEMORY CELL HAVING A FLOATING BODY
An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain,...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
18.09.2014
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Subjects | |
Online Access | Get full text |
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Abstract | An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto. |
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AbstractList | An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto. |
Author | NGUYEN MIKE N TANG SANH D |
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Snippet | An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a... |
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SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | APPARATUS AND METHODS RELATING TO A MEMORY CELL HAVING A FLOATING BODY |
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