CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE

Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to rec...

Full description

Saved in:
Bibliographic Details
Main Authors BLOCK STEFAN, PREUTHEN HERBERT, DIRKS JUERGEN
Format Patent
LanguageEnglish
Published 09.08.2012
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.
Bibliography:Application Number: US201113022824