BUS ARBITRATION APPARATUS

• Main Authors: MAEDA TAKASHI, HASHIMOTO KOUKICHI, MATSUSHITA MASATOSHI, SUMIDA MAMORU
• Format: Patent
• Language: English
• Published: 16.02.2012
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

An arbitration circuit 108 receives a read/write request from a master 101, such as a CPU, in which low latency is required, at a regular interval, such that the master 101 performs memory access with low latency. A remaining band which is not used by the master 101 is allocated to masters 102 and 1...