ARRAY-TYPE PROCESSOR

• Main Authors: IZAWA YOSHITAKA, YABE YOSHIKAZU
• Format: Patent
• Language: English
• Published: 14.08.2008
• Subjects: BASIC ELECTRONIC CIRCUITRY; CALCULATING; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; PHYSICS; PULSE TECHNIQUE; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/reception between the processor elements depending on clock cycle. Each processor element comprises a layout information memory 11 that stores a layout information indicating signal relating to the layout of the paths, a delay adjusting circuit 12 that adjusts the timing of a layout information indicating signal Pin outputted from the layout information memory 11 at every clock cycle, and a wiring connection circuit 13 that changes a path to at least one of the other processor elements (PE) or function unit(s) (a register file unit 14 and an arithmetic logic unit 15 ) based on a layout information indicating signal Pout whose timing has been adjusted.