Method of manufacturing a semiconductor integrated circuit device

A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a...

Full description

Saved in:
Bibliographic Details
Main Authors SALAMA C.ANDRE T, FUJISHIMA NAOTO
Format Patent
LanguageEnglish
Published 27.12.2007
Subjects
Online AccessGet full text

Cover

Loading…
Abstract A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.
AbstractList A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.
Author FUJISHIMA NAOTO
SALAMA C.ANDRE T
Author_xml – fullname: SALAMA C.ANDRE T
– fullname: FUJISHIMA NAOTO
BookMark eNqNyjsOwjAMANAMMPC7gyVmpFLEb6wQiIUJmKvIcYolaleJw_lZOADTW97UjUSFJq65kb00gEbovZTo0Upi6cBDpp5RJRQ0TcBi1CVvFAA5YWGDQB9Gmrtx9O9Mi58zt7ycH6frigZtKQ8eScja572uqn19PGx3dbPe_Le-HLk04A
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US2007298562A1
GroupedDBID EVB
ID FETCH-epo_espacenet_US2007298562A13
IEDL.DBID EVB
IngestDate Fri Jul 19 11:56:38 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US2007298562A13
Notes Application Number: US20070892929
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071227&DB=EPODOC&CC=US&NR=2007298562A1
ParticipantIDs epo_espacenet_US2007298562A1
PublicationCentury 2000
PublicationDate 20071227
PublicationDateYYYYMMDD 2007-12-27
PublicationDate_xml – month: 12
  year: 2007
  text: 20071227
  day: 27
PublicationDecade 2000
PublicationYear 2007
RelatedCompanies FUI ELECTRIC CO., LTD
RelatedCompanies_xml – name: FUI ELECTRIC CO., LTD
Score 2.6859014
Snippet A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM (trench lateral power MOSFET) and one or more planar...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Method of manufacturing a semiconductor integrated circuit device
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071227&DB=EPODOC&locale=&CC=US&NR=2007298562A1
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1da8IwFL2IG9veNrexDzcCG30ra6tt7YMMbS0yqMq0wzdJmhSErRXbsr-_m2CdTz4EQgIhH9zcnOSeE4BXO3HM1DCFzqmLAIXbXPeEmeqeyxH2pIbNuASK0cQZx92Ppb1swHfNhVE6ob9KHBEtKkF7L9V-vfm_xApUbGXxxtZYlL-Hi36g1ejYNS3L1YJhfzSbBlNf8_1-PNcmn6rO8nro7QeIlU7kQVoq7Y--hpKXsjl0KuElnM6wvay8gobIWnDu13-vteAs2j15Y3ZnfcU1DCL13TPJU_JDs0pyEhTJkFBSyBj3PJPirfmW7DUgOEnW26Ral4QLuSXcwEs4WvhjHfuy2g99Fc8PO965hWaWZ-IOCHUYY6ZAZ27RrtthHqNyOQzPSHoJpntoH2vp4Xj1I1yoO0xTUnfa0Cy3lXhC51uyZzVnf5M_ib8
link.rule.ids 230,309,786,891,25594,76906
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1da8IwFL2IG3Nvm9vYh9sCG30ra6tt7YMMbS1usypTh2_SNCkUtlbayv7-boI6n3wIhARCPri5Ock9JwDPZmTpsaZzlYU2AhRmMtXheqw6NkPYE2smZQIoBiNrMG-9L8xFBb63XBipE_orxRHRoiK091Lu16v_SyxPxlYWLzTBouzVn3U8ZYuObd0wbMXrdfqTsTd2FdftzKfK6FPWGU4bvX0XsdKRLfR5xeHpqyd4Kat9p-KfwfEE20vLc6jwtA41d_v3Wh1Ogs2TN2Y31ldcQDeQ3z2TLCY_YboWnARJMiQhKUSMe5YK8dYsJzsNCEaiJI_WSUkYF1vCJTz5_Zk7ULEvy93Ql_PpfsebV1BNs5RfAwktSqnO0ZkbYctuUoeGYjk0R4vaEaYbaBxq6fZw9SPUBrNguBy-jT7u4FTeZ-qCxtOAapmv-T064pI-yPn7Ay0RjKw
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Method+of+manufacturing+a+semiconductor+integrated+circuit+device&rft.inventor=SALAMA+C.ANDRE+T&rft.inventor=FUJISHIMA+NAOTO&rft.date=2007-12-27&rft.externalDBID=A1&rft.externalDocID=US2007298562A1