Smart verify for multi-state memories

The present invention presents a "smart verify" technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed whil...

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Bibliographic Details
Main Authors FONG YUPIN K, GUTERMAN DANIEL C, GONGWER GEOFFREY S
Format Patent
LanguageEnglish
Published 18.05.2006
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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