Data synchronization arrangement

• Main Authors: REICHEL NORBERT, GOLLER JOERG
• Format: Patent
• Language: English
• Published: 15.09.2005
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A data synchronization arrangement is provided that is fail-safe and allows high-speed operation. Clocked data are exchanged between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. The data synchronization arrangement comprises a buffer memory with a predetermined limited number of memory locations each of which has a data write port and a data read port. A write select multiplexer has a data input receiving an input data stream synchronized with the clock from a first clock domain, one data output for each of said memory locations and connected to a respective data write port, and one write select input for each data output. A read select multiplexer has one data input for each of the memory locations and connected to a respective data read port, one read select input for each data input, and a data output supplying an output data stream synchronized with the clock from a second clock domain. A write select shift register has a number of stages corresponding to the predetermined number of memory locations and an output stage looped back to an input stage, each stage having an output connected to a respective one of the write select inputs of the write select multiplexer. The write select shift register is clocked with the clock from the first clock domain. A read select shift register has a number of stages corresponding to the predetermined number of memory locations, each stage having an output connected to a respective one of the read select inputs of the read select multiplexer. The read select shift register is clocked with the clock from the second clock domain. A bit synchronization circuit is provided for loading each shift register with a bit pattern that contains only one high logic value, the bit patterns in the shift registers having a relative offset. In operation, a data input stream synchronized with the clock of the first clock domain is applied to the data input of the write select multiplexer and a data output stream synchronized with the clock of the second clock domain is taken from the data output of the read select multiplexer.