Register without restriction of number of mounted memory devices and memory module having the same

First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of 1/2 of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of singals which temporarily has two times. For ex...

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Bibliographic Details
Main Authors IKEDA HIROAKI, SUGANO TOSHIO, IIZUKA TAKUO, NISHIO YOJI, SHIBATA KAYOKO, SORIMACHI MASAYUKI, FUNABA SEIJI
Format Patent
LanguageEnglish
Published 13.02.2003
Edition7
Subjects
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