Fabrication method of semiconductor integrated circuit device

• Main Authors: ABE HISAHIKO, TSUCHIYAMA HIROFUMI, NISHIGUCHI TAKASHI, HIYAMA MASAKI, NAKABAYSHI SHINICHI
• Format: Patent
• Language: English
• Published: 24.10.2002
• Edition: 7
• Subjects: ADHESIVES; BASIC ELECTRIC ELEMENTS; CHEMISTRY; DRESSING OR CONDITIONING OF ABRADING SURFACES; DYES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS; GRINDING; MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FORELSEWHERE; METALLURGY; MISCELLANEOUS APPLICATIONS OF MATERIALS; MISCELLANEOUS COMPOSITIONS; NATURAL RESINS; PAINTS; PERFORMING OPERATIONS; POLISHES; POLISHING; POLISHING COMPOSITIONS OTHER THAN FRENCH POLISH; SEMICONDUCTOR DEVICES; SKI WAXES; TRANSPORTING

The subject of the present invention is to reduce micro scratches by applying chemical-mechanical polishing. A polishing slurry is diluted with deionized water immediately before it is supplied in a gap between a polishing pad and the surface to be polished of a wafer. By diluting the polishing slurry with deionized water to increase its volume, the concentration of coagulated particles contained in the polishing slurry can be lowered. For a mixture ratio of the polishing slurry and deionized water, about 1 (polishing slurry): 1-1.2 (deionized water) is used and the concentration of silica contained in the diluted polishing slurry is adjusted to about 3-9 weight %, preferably about 4-8 weight % and more preferably about 8 weight %.