Viterbi decoder with high speed processing function

• Main Authors: YAGI YOSHIHARU, TAKAHASHI HIDEAKI
• Format: Patent
• Language: English
• Published: 22.11.2001
• Edition: 7
• Subjects: BASIC ELECTRONIC CIRCUITRY; CALCULATING; CODE CONVERSION IN GENERAL; CODING; COMPUTING; COUNTING; DECODING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS

A Viterbi decoder includes a path metric memory, a path memory, a branch metric generating section, an ACS (add compare and select) unit, a write section and a read section. The branch metric generating section generates branch metric data at times. The ACS unit calculates new path metric data from path metric data inputted thereto and the branch metric data at the times supplied from the branch metric generating section and determines path selection data for the new path metric data. The write section writes the new path metric data and the path selection data in the path metric memory and the path memory, respectively. The read section which reads out the path metric data from the path metric memory to output to the ACS unit.