Low latency matrix multiply unit
Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. The matrix multiply unit may include cells arranged in columns of the systolic array. Two chains of weight shift registers per column of the systolic array are in the matrix multiply un...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
21.05.2024
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Subjects | |
Online Access | Get full text |
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