1D vertical edge blocking (VEB) via and plug

• Main Authors: Harper, Michael, Sivakumar, Swaminathan, Rich, Suzanne S, Nyhus, Paul, Schenker, Richard E, Haran, Mohit K, Guler, Leonard P, Ward, Curtis, Patel, Reken, Wallace, Charles H
• Format: Patent
• Language: English
• Published: 30.04.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein t...