SRAM architecture

The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read...

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Bibliographic Details
Main Authors Neves Rodrigues, Joachim, Mohammadi, Babak
Format Patent
LanguageEnglish
Published 26.12.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:The present invention relates generally to the field of semiconductor memories and in particular to memory cells comprising a static random access memory (SRAM) bitcell (100). Leakage current in the read path is reduced by connecting a read access transistor terminal either to GND or VDD during read access or write access and idle state. The SRAM cell inverters may be asymmetrical in size. The memory may comprise various boost circuits to allow low voltage operation or application of distinguished supply voltages.
Bibliography:Application Number: US202217933933