Memory supporting multiple types of operations

A method of operating a memory comprising a plurality of memory planes is disclosed. Each memory plane includes at least one corresponding memory array. The method includes, for each memory plane of the plurality of memory planes, generating (i) a corresponding plane ready (PRDY) signal indicating a...

Full description

Saved in:
Bibliographic Details
Main Authors Hung, Shuo-Nan, Liu, Chien-Hsin, Kuo, Nai-Ping
Format Patent
LanguageEnglish
Published 29.08.2023
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:A method of operating a memory comprising a plurality of memory planes is disclosed. Each memory plane includes at least one corresponding memory array. The method includes, for each memory plane of the plurality of memory planes, generating (i) a corresponding plane ready (PRDY) signal indicating a busy or a ready state of the corresponding memory plane, and (ii) a corresponding plane array ready (PARDY) signal indicating a busy or a ready state of the corresponding memory array of the corresponding memory plane, such that a plurality of PRDY signals and a plurality of PARDY signals are generated corresponding to the plurality of memory planes. Execution of a memory command for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PARDY signals.
Bibliography:Application Number: US202117535021