Barrier structure configured to increase performance of III-V devices

• Main Authors: Yeh, Chia-Ling, Tsai, Chun Lin, Yu, Jiun-Lei Jerry, Chen, Ching Yu, Chen, Po-Chih, Wang, Yun-Hsiang
• Format: Patent
• Language: English
• Published: 01.08.2023
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, w...