Authenticated debug for computing systems
An apparatus includes one or more functional circuits, a debug circuit configured to implement one or more debug features for the one or more functional circuits, and a validation circuit. The validation circuit is configured to receive a request to access debug features, and to send an identificati...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
11.10.2022
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Subjects | |
Online Access | Get full text |
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