Level shifter circuit applied to display apparatus
A level shifter circuit includes an input terminal, a first output terminal, a second output terminal, an output stage, a first control bias unit, a second control bias unit, and an output stage. The input stage includes a first transistor and a second transistor, and their gates are coupled to the...
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Format | Patent |
Language | English |
Published |
24.05.2022
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Subjects | |
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Abstract | A level shifter circuit includes an input terminal, a first output terminal, a second output terminal, an output stage, a first control bias unit, a second control bias unit, and an output stage. The input stage includes a first transistor and a second transistor, and their gates are coupled to the input terminal. The first control bias unit includes a third transistor and a fourth transistor coupled to the first transistor and second transistor respectively and their gates are controlled by a first bias. The output stage includes a fifth transistor and a sixth transistor coupled to the third transistor and fourth transistor respectively and their gates are coupled to the first output terminal and second output terminal. The second control bias unit includes a seventh transistor and an eighth transistor coupled to the fifth transistor and sixth transistor respectively and their gates are controlled by a second bias. |
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AbstractList | A level shifter circuit includes an input terminal, a first output terminal, a second output terminal, an output stage, a first control bias unit, a second control bias unit, and an output stage. The input stage includes a first transistor and a second transistor, and their gates are coupled to the input terminal. The first control bias unit includes a third transistor and a fourth transistor coupled to the first transistor and second transistor respectively and their gates are controlled by a first bias. The output stage includes a fifth transistor and a sixth transistor coupled to the third transistor and fourth transistor respectively and their gates are coupled to the first output terminal and second output terminal. The second control bias unit includes a seventh transistor and an eighth transistor coupled to the fifth transistor and sixth transistor respectively and their gates are controlled by a second bias. |
Author | Lin, Po-Cheng Lin, Yu-Chun |
Author_xml | – fullname: Lin, Yu-Chun – fullname: Lin, Po-Cheng |
BookMark | eNrjYmDJy89L5WQw8kktS81RKM7ITCtJLVJIzixKLs0sUUgsKMjJTE1RKMlXSMksLshJrAQJJRYllpQW8zCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSS-NBgQ0NjE0MLC0MnI2Ni1AAA254uKg |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences Education Physics |
ExternalDocumentID | US11341881B2 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_US11341881B23 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 15:19:03 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_US11341881B23 |
Notes | Application Number: US201615013435 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220524&DB=EPODOC&CC=US&NR=11341881B2 |
ParticipantIDs | epo_espacenet_US11341881B2 |
PublicationCentury | 2000 |
PublicationDate | 20220524 |
PublicationDateYYYYMMDD | 2022-05-24 |
PublicationDate_xml | – month: 05 year: 2022 text: 20220524 day: 24 |
PublicationDecade | 2020 |
PublicationYear | 2022 |
RelatedCompanies | Raydium Semiconductor Corporation |
RelatedCompanies_xml | – name: Raydium Semiconductor Corporation |
Score | 3.4071078 |
Snippet | A level shifter circuit includes an input terminal, a first output terminal, a second output terminal, an output stage, a first control bias unit, a second... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CRYPTOGRAPHY DISPLAY EDUCATION PHYSICS SEALS |
Title | Level shifter circuit applied to display apparatus |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220524&DB=EPODOC&locale=&CC=US&NR=11341881B2 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_G_HzTquj8IIL0rbi2ceseirB2Y4j7wK2yt5G0KatIW9YO8b83Fzvni75eIFwSfneX5O53AHe23e6EZsyMqC2vq1SY3HBiyzTikAkmHbIw1UkPR61BQJ_mD_MavG1qYRRP6IciR5SICiXeS2Wv8-0jlq9yK4t7nkhR9tifub5e3Y6xatSiut91e5OxP_Z0z3ODqT56cU0kLnMcsyvN9Q6G0ciz33vtYlVK_tul9I9gdyJnS8tjqIlUgwNv03lNw07KVdaFBvvD6vNbgz2VrRkWUlghsjgB6xmzfkixTLDZNwmTVbhOSsK-g0tSZiRKivydfaIIab7XxSnc9nszb2BIlRY_618E06329hnU0ywV50CY1eKUS0DasUMZ54zKaIQ3O00s929G4gIaf8_T-G_wEg5xL_GT3KJXUC9Xa3EtfW_Jb9SmfQH-Ooh9 |
link.rule.ids | 230,309,786,891,25594,76903 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR3LSsNAcCj1UW8aFa2vCJJbMI-1TQ9BaNJStS9sK72F3XSDEUlKkyD-vbNrar3odRaG2VnmtfMCuLHtZis0I6ovmhiuEm4y3YksU49CyikaZG7Klx4MG70ZeZzfzSvwtu6FkXNCP-RwRJSoEOU9l_p6ufnE8mVtZXbLYgSl992p62tldCy6Ri2i-W23Mx75I0_zPHc20YbPrikGlzmO2UZ1vdXEkFCGSi9t0ZWy_G1SuvuwPUZsSX4AFZ4oUPPWm9cUsUm5rLpQYHdQJr8V2JHVmmGGwFIis0Ow-qLqR81eY7HsWw3jVVjEuUq_nUs1T9VFnC3f6acAiTHfRXYE193O1OvpSFLwc_9gNtlQbx9DNUkTfgIqtRqMMBRIO3IIZYwS9EaY0TJEu7-x4KdQ_xtP_b_DK6j1poN-0H8YPp3BnuCrSJhb5Byq-argF2iHc3YpGfgFhU-LZw |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Level+shifter+circuit+applied+to+display+apparatus&rft.inventor=Lin%2C+Yu-Chun&rft.inventor=Lin%2C+Po-Cheng&rft.date=2022-05-24&rft.externalDBID=B2&rft.externalDocID=US11341881B2 |