Power electronics package and method of manufacturing thereof

• Main Authors: Gowda, Arun Virupaksha, Stoffel, Nancy Cecelia, McConnelee, Paul Alan, Tuominen, Risto Ilkka
• Format: Patent
• Language: English
• Published: 16.11.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An electronics package is disclosed herein that includes a glass substrate having an exterior portion surrounding an interior portion thereof, wherein the interior portion has a first thickness and the exterior portion has a second thickness larger than the first thickness. An adhesive layer is formed on a lower surface of the interior portion of the glass substrate. A semiconductor device having an upper surface is coupled to the adhesive layer, the semiconductor device having at least one contact pad disposed on the upper surface thereof. A first metallization layer is coupled to an upper surface of the glass substrate and extends through a first via formed through the first thickness of the glass substrate to couple with the at least one contact pad of the semiconductor device.