Apparatus and method for managing address collisions when performing vector operations

• Main Authors: Eapen, Jacob, Martinez Vicente, Alejandro, Eyole, Mbou
• Format: Patent
• Language: English
• Published: 28.09.2021
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Address collisions are managed when performing vector operations. A register store stores vector operands. Execution circuitry performs memory access operations to move the vector operands between the register store and memory and data processing operations using the vector operands. The execution circuitry may iteratively execute a vector loop, where during each iteration the execution circuitry executes a sequence of instructions to implement the vector loop. The sequence includes a check instruction identifying a plurality of memory addresses. The execution circuitry responds to the check instruction to determine whether an address hazard condition exists among the plurality of memory addresses. For each iteration of the vector loop, the execution circuitry responds to the check instruction determining an absence of the hazard address condition to employ a default level of vectorization when executing the sequence of instructions to implement the vector loop. But in the presence of the address hazard condition, the execution circuitry employs a reduced level of vectorization to implement the vector loop.