3-dimensional memory device

• Main Authors: Kim, Changbum, Kim, Sunghoon, Kim, Seungyeon
• Format: Patent
• Language: English
• Published: 20.07.2021
• Subjects: ELECTRICITY; INFORMATION STORAGE; PHYSICS; STATIC STORES

A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions.