Gather-scatter cache architecture having plurality of tag and data banks and arbiter for single program multiple data (SPMD) processor

In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wh...

Full description

Saved in:
Bibliographic Details
Main Authors Srinivasan, Srikanth T, Pearce, Jonathan D, Bheda, Rishiraj A, Sheffield, David B, Davare, Abhijit, Cook, Jeffrey J, Sorokin, Anton Alexandrovich
Format Patent
LanguageEnglish
Published 19.01.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online AccessGet full text

Cover

More Information
Summary:In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.
Bibliography:Application Number: US201916364725