Layouts for connecting contacts with metal tabs or vias

The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and...

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Bibliographic Details
Main Authors Nayyar, Neha, Dechene, Daniel J, Pritchard, David C, Kluth, George J
Format Patent
LanguageEnglish
Published 23.06.2020
Subjects
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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Summary:The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.
Bibliography:Application Number: US201715644288