Apparatus and method to prevent integrated circuit from entering latch-up mode

The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distin...

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Bibliographic Details
Main Authors Chang, Shunhua T, Yu, Mickey H, Muhammad, Mujahid, Lu, Xiangxiang, Gebreselasie, Ephrem G
Format Patent
LanguageEnglish
Published 28.04.2020
Subjects
ADVERTISING
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION
BASIC ELECTRIC ELEMENTS
CRYPTOGRAPHY
DISPLAY
EDUCATION
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEALS
SEMICONDUCTOR DEVICES
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Summary:The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.
Bibliography:Application Number: US201816176380