Fan-out semiconductor package

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on...

Full description

Saved in:
Bibliographic Details
Main Authors Kim, Yeong A, Kim, Eun Sil, Kuroyanagi, Akihisa, Myung, Jun Woo
Format Patent
LanguageEnglish
Published 10.12.2019
Subjects
Online AccessGet full text

Cover

Loading…
Abstract A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.
AbstractList A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.
Author Kuroyanagi, Akihisa
Kim, Yeong A
Myung, Jun Woo
Kim, Eun Sil
Author_xml – fullname: Kim, Yeong A
– fullname: Kim, Eun Sil
– fullname: Kuroyanagi, Akihisa
– fullname: Myung, Jun Woo
BookMark eNrjYmDJy89L5WSQdUvM080vLVEoTs3NTM7PSylNLskvUihITM5OTE_lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBVqXmpJfGhwYYGpgYmFsZmTkbGxKgBAKkaJhE
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
ExternalDocumentID US10504836B2
GroupedDBID EVB
ID FETCH-epo_espacenet_US10504836B23
IEDL.DBID EVB
IngestDate Fri Jul 19 14:30:28 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US10504836B23
Notes Application Number: US201816053193
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191210&DB=EPODOC&CC=US&NR=10504836B2
ParticipantIDs epo_espacenet_US10504836B2
PublicationCentury 2000
PublicationDate 20191210
PublicationDateYYYYMMDD 2019-12-10
PublicationDate_xml – month: 12
  year: 2019
  text: 20191210
  day: 10
PublicationDecade 2010
PublicationYear 2019
RelatedCompanies SAMSUNG ELECTRONICS CO., LTD
RelatedCompanies_xml – name: SAMSUNG ELECTRONICS CO., LTD
Score 3.2466028
Snippet A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Fan-out semiconductor package
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20191210&DB=EPODOC&locale=&CC=US&NR=10504836B2
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFD6MKeqbTkU3JxWkb8GuV_pQBk1bhuA23Cp7Gz29gArtWDv8-56EzvmibyGBXE74ziU5-QLwaLlammCRsgRdnZm0DwzJ0jLEFNFBNDCTbJ9TexKbzytr1YGP_VsYyRP6JckRCVEp4b2R-npzOMQKZG5l_YTvVFWNo6UXqG10TMEHhTBq4HvhfBbMuMq5Fy_U6Sv5upYgT7d9UtdHwo0WPPvhmy9epWx-m5ToHI7n1FvZXEAnL3twyvc_r_Xg5KW98KZii736EoZRUrJq1yi1yGevSkHUWm0Vmv4n6YQreIjCJZ8wGmf9s6h1vDhMybiGLgX7-Q0ombi4JB_GcbLCNAlOhT7KDE1HwonhpvYt9P_up_9f4wDOhIBEKsZIu4Nus93lQzKoDd5LSXwD6HB5HQ
link.rule.ids 230,309,786,891,25594,76904
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5KFetNq6LVagTJLZg2L3IIQl5EbdNiE-ktZPKAKiSlSfHvOxtS60Vvyy7sk29mv93ZbwEeFF1MYswTIUZ9LMi0DgKSpxUQE0QNUcK0Ufv0VS-UX5bKsgMfu7cwjU7oVyOOSIhKCO91Y6_X-0Msu4mtrB5xRVnlkxsYNt-yYyIfRGF42zSc-cyeWbxlGeGC999or6sw8XTVJHN9oBElZDr7zrvJXqWsf7sU9wQO51RbUZ9CJyv60LN2P6_14WjaXnhTssVedQZDNy6EcltzFYtnLwsm1FpuOOr-J9mEc7h3ncDyBGon-hlUFC72XZIuoEtkP7sELmUXl7SH0bQ0l2WCUz4epZI4RsKJpCfqFQz-rmfwX-Ed9LxgOokmz_7rNRyzyWJhGSPxBrr1ZpsNybnWeNvMyje4H3wI
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Fan-out+semiconductor+package&rft.inventor=Kim%2C+Yeong+A&rft.inventor=Kim%2C+Eun+Sil&rft.inventor=Kuroyanagi%2C+Akihisa&rft.inventor=Myung%2C+Jun+Woo&rft.date=2019-12-10&rft.externalDBID=B2&rft.externalDocID=US10504836B2