Short address mode for communicating waveform

Systems, methods, and apparatus for data communication are provided. A device operating as a bus master may be detect one or more slaves on a serial bus supporting a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address. The...

Full description

Saved in:
Bibliographic Details
Main Authors Kim, Kyu Hak, Bu, Guangming
Format Patent
LanguageEnglish
Published 06.08.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Systems, methods, and apparatus for data communication are provided. A device operating as a bus master may be detect one or more slaves on a serial bus supporting a shortened address mode for receiving a waveform having at least one of a shortened slave address or a shortened register address. The bus master may then calculate a number of slave address bits needed to address the one or more slaves in a binary form based on a quantity of the one or more slaves and generate shortened slave addresses for the one or more slaves, respectively. A length of each shortened slave address is the number of slave address bits. The bus master may then assign a generated shortened slave address to each of the one or more slaves and send the waveform to a slave via the serial bus using an assigned shortened slave address.
Bibliography:Application Number: US201715658748