Adaptive pattern filtering for clock and data recovery to minimize interaction with decision feedback equalization
Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to levels that can corrupt the timing recovery. Embodiments of the systems and methods provide for a phase detector that selectively suppresses...
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| Main Authors | , |
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| Format | Patent |
| Language | English |
| Published |
16.07.2019
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| Subjects | |
| Online Access | Get full text |
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| Abstract | Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to levels that can corrupt the timing recovery. Embodiments of the systems and methods provide for a phase detector that selectively suppresses timing information based on the logic level states of the Qp and Qm data samples associated with the received signal. |
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| AbstractList | Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to levels that can corrupt the timing recovery. Embodiments of the systems and methods provide for a phase detector that selectively suppresses timing information based on the logic level states of the Qp and Qm data samples associated with the received signal. |
| Author | Fortin, Guillaume Huss, Scott David |
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| RelatedCompanies | Cadence Design Systems, Inc |
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| Snippet | Systems and methods disclosed herein provide for adaptively applying pattern filters so that the edges are discarded only when the DFE feedback has adapted to... |
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| SubjectTerms | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| Title | Adaptive pattern filtering for clock and data recovery to minimize interaction with decision feedback equalization |
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