Cache memory and operation method thereof

Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each...

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Bibliographic Details
Main Authors Kwon, Young-Su, Han, Jin Ho, Byun, Kyung Jin, Eum, Nak Woong
Format Patent
LanguageEnglish
Published 15.01.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.
Bibliography:Application Number: US201615241902